Hardware engineer working across RTL design, verification, FPGAs, ML accelerators, and VLSI/EDA.

Most of what I've built over the past year follows the same arc: train a model, generate the RTL, fight it through timing closure, then prove the hardware and the software agree bit for bit.

That last step is the part I find most interesting, and the part most projects skip. It's easy to build something that produces plausible output. Establishing that a design produces the correct output — across the netlist, at speed, on real silicon rather than only in simulation — is a different and much less forgiving problem.

RTL design, design verification, FPGAs, ML accelerators, and VLSI/EDA — weighted equally. Most of my projects sit across several at once: an accelerator is an RTL problem, a verification problem, and a place-and-route problem before it's an ML problem. I'm drawn to the software side of hardware too — toolchains, codegen, automation. My favorite thing I've built is a checkpoint-to-Verilog generator, a tool for making hardware rather than a piece of hardware, and that appeals to me more than any single design has.

I'm in the Canfield Business Honors Program alongside ECE. Away from all of it: basketball, badminton, fantasy football, blogging, and travel. Fluent in Kannada, basic French.